Usually, the gate of a conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a planar structure. When the critical dimension of the MOSFET is shrunk to a certain value, the short channel effects of the MOSFET become more prominent. The sub-threshold current and the gate leakage current are increased. Thus, the performance of the MOSFET is adversely affected. It is often difficult to further reduce the critical dimension of the conventional MOSFET.
The multiple-gate MOSFET has a better gate control ability; and is able to inhibit the short channel effects. Fin Field Effect Transistor (FinFET) devices are a typical type of multiple-gate MOSFETs. The FinFET devices are often formed on a bulk silicon substrate, or on a Silicon-On-Insulation (SOI) substrate. The FinFET devices are able to match certain technical requirements.
Under certain conditions, it requires the FinFET devices to have variable threshold voltages. That is, it requires the PMOS transistors and the NMOS transistors in a FinFET device to have different threshold voltages (multiple-VT).
However, it may be difficult for the existing techniques to form a FinFET device having PMOS transistors and NMOS transistors with different threshold voltages. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.